Conventional semiconductor fabrication processes have reduced device geometries in the x, y and z directions so as to facilitate the fabrication of relatively dense memory cells. Memories having higher densities, however, are vulnerable to increased defect rates (e.g., defects per unit area). To salvage memory that otherwise would be lost due to defects, memory designers usually include extra memory to replace defective memory.
A common approach to salvaging memory divides a memory into multiple, equivalently-sized groupings in which each row in a grouping is a separate, isolated collection of memory cells. A Flash memory array, for example, can be partitioned into four equal areas. By partitioning memory in this manner, a memory is less susceptible to fatal defects that otherwise render the entire memory (i.e., the aggregate of all groupings) inoperative. To illustrate, consider that a defect in an unpartitioned memory causes an entire column to fail. As such, the entire memory array is unusable. But if the memory is partitioned, the defect will at most affect only the grouping in which the defect resides. This allows the memory to remain usable, albeit with less memory capacity. To recover lost memory, some memories traditionally include extra rows in each grouping to replace a limited number of rows having defects. These extra rows are typically selected by programming bits stored in non-volatile registers to indicate which one of a number of substitute alternate rows will be used to replace a defective row. Therefore, each grouping is usually associated with a dedicated set of non-volatile registers. Further, each grouping usually includes an extra decoder to uniquely select each of the extra rows.
While this approach is functional, it has its drawbacks. First, extra rows, non-volatile registers, and extra decoders, if used, collectively consume amounts of surface area in traditional memory architectures. This, in turn, increases the die size (i.e., in the X and Y dimensions). Second, memory designers are typically faced with deciding how many extra memory rows to add to each grouping, especially since memory fabrication processes can randomly cause any number of unforeseen defects. If a memory designer adds too many extra rows, then any unused memory that does not remedy a defect will unnecessarily increase the die size. But if the memory designer adds too few extra rows, then the memory array cannot support its intended memory capacity, which decreases the yield of good memories. Third, conventional row replacement techniques, as described above, do not usually adapt to the different defects rates that each grouping experiences. For example, consider that each of eight groupings includes five extra rows to replace five defective rows, if necessary. Next, consider that a fabrication process introduces defects in each memory as follows: one of the eight groupings has six defective rows while the other groupings have two defective rows. As is common, the extra rows in the other groupings cannot be used to replace the sixth defective row, and, thus, that row renders its grouping inoperative. Fourth, accessing the extra rows using conventional row replacement techniques can ordinarily have longer access times than accessing the main array, especially if the detection of defects and implementation of the extra rows are performed, for example, serially.
There are continuing efforts to improve techniques, systems and devices for compensating for defects in memory.
Like reference numerals refer to corresponding parts throughout the several views of the drawings. Note that most of the reference numerals include one or two left-most digits that generally identify the figure that first introduces that reference number. Although the Drawings depict various examples of the invention, the invention is not limited by the depicted examples. Furthermore, the depictions are not necessarily to scale.